1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device with neighboring n- and p-type regions formed in a semiconductor substrate, which is applicable to fabrication of bipolar transistors on a semiconductor integrated circuit device.
2. Description of the Prior Art
In recent years, with fabrication of a semiconductor integrated circuit device containing bipolar transistors, several researches and developments have been made into formation of n.sup.+ - and p.sup.+ -type buried regions in the same process step so that the number of photolithography processes is reduced to unity.
A conventional method of this sort thus developed is shown in 1A to 1D and a semiconductor integrated circuit device fabricated by this method is shown in FIG. 2.
In this method, first, as shown in FIG. 1A, a silicon dioxide (SiO.sub.2) film 44 with a thickness of 500 to 1000 nm is formed on a p-type semiconductor substrate 31. Then, a photoresist film 45 is formed on the SiO.sub.2 film 44 and is patterned to have a rectangular window 55 by a photolithography process.
Using the photoresist film 45 thus patterned as a mask, the SiO.sub.2 film 44 is selectively removed through a wet etching process using hydrofluoric acid, so that another rectangular window 54 is formed in the film 44, as shown in FIG. 1A. The window 54 is larger than the window 55 to contain the window 55 therein.
Next, the photoresist film 45 is removed and then, the substrate 31 is oxidized in the window 54 so that a thin SiO.sub.2 film 46 with a thickness of 30 to 50 nm is selectively formed on the exposed part of the substrate 31, as shown in FIG. 1B.
Using the SiO.sub.2 film 44 with the window 54 as a mask, ionized arsenic (As) atoms are selectively implanted into the substrate 31 through the thin SiO.sub.2 film 46 in the window 54 with a dose of about 5.times.10.sup.15 cm.sup.-2, which is termed a first ion-implantation process. The substrate 31 thus arsenic-implanted is then annealed at a temperature of about 1140.degree. C. for about 210 minutes to diffuse the doped arsenic atoms, so that the atoms will be electrically active. The arsenic atoms thus implanted and diffused form an n.sup.+ -type buried region 32 inside the substrate 31, as shown in FIG. 1C. The region 32 is rectangular in plan shape corresponding to the window 54.
After the SiO.sub.2 film 44 and 46 are removed entirely from the substrate 31 by a wet etching process, a thin SiO.sub.2 film 47 is formed again on the substrate 31 to cover the buried region 32, as shown in FIG. 1C.
Then, ionized boron (B) atoms are implanted into the entirety of the substrate 31 through the thin SiO.sub.2 film 47 with a dose of about 5.times.10.sup.13 cm.sup.-2, which is termed a second ion-implantation process. The dose of the process is much lower than that of the first ion-implantation process.
The substrate 31 thus boron-implanted is then annealed at a temperature of about 1000.degree. C. for about 60 minutes to diffuse the boron atoms, so that the atoms will be electrically active. The boron atoms thus implanted and diffused form a p.sup.+ -type buried region 33 inside the substrate 31, as shown in FIG. 1D. Since the boron atoms are implanted into the entirety of the substrate 31, the p.sup.+ -type buried region 33 is formed to be overlaid with the n.sup.+ -type buried region 32.
Thus, the n.sup.+ -type buried region 32 is subjected to the above boron implantation. However, since the boron implantation is sufficiently low in dose or doping concentration compared with the arsenic implantation, the n.sup.+ -type buried region 32 is scarcely affected by the boron implantation. Therefore, the n.sup.+ -type buried region 32 remains as it was, and the resultant p.sup.+ -type buried regions 33 is produced outside the n.sup.+ -type buried region 32 so as to surround the region 32, as shown in FIG. 1D.
After the SiO.sub.2 film 47 is removed, an n.sup.- -type epitaxial layer 34 is grown on the surface of the substrate 31 to cover the n.sup.+ - and p.sup.+ -type buried regions 32 and 33, as shown in FIG. 2.
Then, in the epitaxial layer 34, a p.sup.+ -type diffusion region 43 as a channel stop is selectively formed along the p.sup.+ -type buried region 33 to be contacted with the region 33.
After a field SiO.sub.2 film 35 for lateral isolation is selectively formed on the epitaxial layer 34, a p.sup.+ -type extrinsic base region 36 and a p-type intrinsic base region 37 of an npn-type bipolar transistor are selectively formed in the epitaxial layer 34 to be contacted with each other, as shown in FIG. 2. The both base regions 36 and 37 are in contact with the field SiO.sub.2 film 35, respectively, and are placed over the n.sup.+ -type buried region 32.
An n.sup.+ -type emitter region 38 of the transistor is formed in the epitaxial layer 34 to be surrounded by the intrinsic base region 37. The part of the epitaxial layer 34 under the intrinsic base regions 37 act as a collector region of the transistor.
A first dielectric film 40a is formed on the exposed epitaxial layer 34 and the field SiO.sub.2 film 35. Then, a polysilicon film 39 as an emitter contact is selectively formed on the film 40a. The polysilicon film 39 is in contact with the emitter region 38 through a contact hole of the film 40a.
A second dielectric film 40b is formed on the first dielectric film 40a and the polysilicon film 39, and a third dielectric film 40c is formed on the second dielectric film 40b.
A metal film is then deposited on the third dielectric film 40c and is patterned to make an emitter electrode 41 and a base electrode 42. The emitter electrode 41 is in contact with the polysilicon film 39 through contact holes of the second and third dielectric films 40b and 40c. The base electrode 42 is in contact with the extrinsic base region 36 through contact holes of the first, second and third dielectric films 40a, 40b and 40c.
A collector electrode (not shown) is also formed on the third dielectric film 40c to be in contact with the epitaxial layer 34 as the collector region through contact holes of the first, second and third dielectric films 40a, 40b and 40c.
Thus, the conventional npn-type bipolar transistor shown in FIG. 2 is obtained. The n.sup.+ -type buried region 32 has an action to reduce the collector resistance. On the other hand, the p.sup.+ -type buried region 33 has an action to electrically separate the n.sup.+ -type buried region 32 from an n.sup.+ -type buried region (not shown) of another bipolar transistor adjacent to this transistor concerned. With the bipolar transistor fabricated by the above conventional method, the n.sup.+ -type buried region 32 is positioned closely to the p.sup.+ -type buried region 33 in the substrate 31 and the epitaxial layer 34. Therefore, when the layout or positional arrangement of the field SiO.sub.2 film 35 and the n.sup.+ -type buried region 32 is designed with a slight or no margin of stacking error, the edge of the p.sup.+ -type extrinsic base region 36, which is defined by the boundary of the field SiO.sub.2 film 35, will be formed closely to the opposing edge of the p.sup.+ -type buried region 33, as shown in FIG. 2. As a result, there is a problem that electric-current leak or short tends to occur between the p.sup.+ -type extrinsic base region 36 and the p.sup.+ -type buried regions 33, which remarkably reduces the fabrication yield of the bipolar transistor.
To solve the problem, as shown in FIG. 3, the n.sup.+ -type buried region 32 may be designed to be laterally expanded so that the above margin of stacking error between the edge of the p.sup.+ -type extrinsic base region 36 and the opposing edge of the p.sup.+ -type buried region 33 becomes sufficiently large.
In this case, however, there arises another problem that the collector capacitance tends to increase with the expansion in area of the n.sup.+ -type buried region 32, resulting in decrease in operation speed of the bipolar transistor.